Package architecture is moving beyond the traditional uniplanar arrangement of a single integrated circuit (IC) chip. Three-dimensional (“3D”) architectures are generating greater interest and offer many advantages over uniplanar architectures. 3D architectures or 3D chip stacks (sometimes referred to herein as “3D stack”, “3D IC”, “stack of dies”) encompass architectures where chips are positioned on more than one plane and may be integrated both horizontally and vertically into a single package. Nevertheless, 3D ICs present a variety of challenges for verifying the functionality of the individual chips in the circuit. Verification of connections between chips in a 3D IC may be labor and resource-intensive and involve long testing and verification times.
A typical current 3D IC verification methodology system is shown as system 100 in FIG. 1. Four individual dies, Die A 102, Die B 103, Die C 104, and Die D 105 are stacked in a 3D IC stack operatively connected to a test bench 101 such that only Die A is directly connected to the test bench and each of the other dies in the stack, which are separated by inter-die interfaces 107, 108, and 109, are not directly connected to the test bench. Peripheral drivers 106 are also attached to the test bench 101. The interactions between Dies A through D are shown by arrows 1A, 1B, 1C, 1D, 2B, 2C, 2D, 3C, 3D, and 4D. In order to perform functional verification of Die A 102 using the test bench 101 and the peripheral drivers 106, the interactions between all of the dies in the stack are taken into account.